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256/512/1k/2k/4k/8k x9 x2 double sync ? fifos cy7c4801/4811/4821 cy7c4831/4841/4851 cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-06005 rev. ** revised january 15, 1997 cy7c4831/4 1 features double high speed, low power, first-in first-out (fifo) memories ? double 256 x 9 (cy7c4801) double 512 x 9 (cy7c4811) double 1k x 9 (cy7c4821) double 2k x 9 (cy7c4831) double 4k x 9 (cy7c4841) double 8k x 9 (cy7c4851) functionally equivalent to two cy7c4201/4211/4221/ 4231/4241/4251 fifos in a single package 0.65 micron cmos for optimum speed/power high-speed 100-mhz operation (10 ns read/write cycle times) offers optimal combination of large capacity, high speed, design flexibility, and small footprint fully asynchronous and simultaneous read and write operation four status flags per device: empty, full, and program- mable almost empty/almost full low power ? i cc1 = 60ma output enable (oea /oeb ) pins depth expansion capability width expansion capability space-saving 64-pin tqfp pin compatible and functionally equivalent to idt72801, 72811, 72821, 72831, 72841,72851 functional description the cy7c48x1 are double high-speed, low-power, first-in first-out (fifo) memories with clocked read and write interfac- es. all are 9 bits wide and operate as two separate fifos. the cy7c48x1 are pin-compatible to idt728x1. programmable features include almost full/almost empty flags. these fifos provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiprocessor interfac- es, and communications buffering. these fifos have two independent sets of 9-bit input and output ports that are controlled by separate clock and enable signals. the input port is controlled by a free-running clock (wclka,wclkb) and two write-enable pins (wena1 , wena2/lda , wenb1 , wenb2/ldb ). when (wena1 ,wenb1 ) is low and (wena2/lda , wenb2/ldb ) is high, data is written into the fifo on the rising edge of the (wclka,wclkb) signal. while (wena1 , wena2/lda , wenb1 , wenb2/ldb ) is held active, data is continually written into the fifo on each wclka, wclkb cycle. the output port is controlled in a similar manner by a free-running read clock (rclka, rclkb) and two read-en- able pins ((rena1 ,renb1 ), (rena2 ,renb2 )). in addition, the cy7c48x1 has output enable pins (oea , oeb ) for each fifo. the read (rclka, rclkb) and write (wclka, wclkb) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications. clock frequencies up to 100 mhz are achievable. depth expansion is possible using one enable input for system control, while the other enable is controlled by expansion logic to direct the flow of data. the cy7c48x1 provides two sets of four different status pins: empty, full, almost empty, almost full. the almost empty/almost full flags are programmable to single word granularity. the programmable flags default to empty+7 and full ? 7. the flags are synchronous, i.e., they change state relative to either the read clock (rclka,rclkb) or the write clock (wclka,wclkb). when entering or exiting the empty and almost empty states, the flags are updated exclusively by the (rclka,rclkb). the flags denoting almost full, and full states are updated exclusively by (wclka,wclkb) the syn- chronous flag architecture guarantees that the flags maintain their status for at least one cycle all configurations are fabricated using an advanced 0.65 n-well cmos technology. input esd protection is greater than 2001v, and latch-up is prevented by the use of guard rings.
cy7c4801/4811/4821 cy7c4831/4841/4851 document #: 38-06005 rev. ** page 2 of 23 logic block diagram 48x1 ? 1 three ? state output register read control b flag logic write control write pointer b read pointer b reset logic flag program register db 0-8 rclkb efa paea pafa qb 0-8 rsa oeb ram array a 256 x9 . . 8k x 9 renb1 renb2 ffa write control write pointer a wena1 wclka wena2/lda rsb wenb1 wclkb wenb2/ldb ram array b . . 8k x 9 read control a read pointer a rclka rena1 rena2 input register da 0-8 qa 0-8 lda ldb efb paeb pafb ffb oea input register three ? state output register 256 x9 qb 6 tqfp top view 48x1 ? 1 qa 2 qa 3 qa 4 qa 5 qa 6 qa 7 qa 8 v cc wena2/lda wclka wena1 rsa da 8 da 7 da 6 qa 1 qb 2 qb 3 qb 4 qb 5 qb 7 qb 8 gnd rena1 rclka rena2 oea efa ffa qa 0 da 5 da 3 da 2 da 1 da 0 pafa paea wenb2/ldb wclkb wenb1 rsb db 8 db 7 db 6 db 5 qb 0 ffb efb oeb renb2 rclkb renb1 gnd v cc paeb pafb db 0 db 1 db 2 db 3 db 4 qb 1 da 4 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 cy7c4801 cy7c4811 cy7c4821 cy7c4831 cy7c4841 cy7c4851 pin configuration
cy7c4801/4811/4821 cy7c4831/4841/4851 document #: 38-06005 rev. ** page 3 of 23 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ....................................... ? 65 c to +150 c ambient temperature with power applied .................................................... ? 55 c to +125 c supply voltage to ground potential .................? 0.5v to +7.0v dc voltage applied to outputs in high z state .....................................................? 0.5v to +7.0v dc input voltage .................................................? 0.5v to +7.0v output current into outputs (low) .............................20 ma static discharge voltage ........................................... >2001v (per mil-std-883, method 3015) latch-up current..................................................... >200 ma selection guide 7c48x1-10 7c48x1-15 7c48x1-25 7c48x1-35 maximum frequency (mhz) 100 66.7 40 28.6 maximum access time (ns) 8 10 15 20 minimum cycle time (ns) 10 15 25 35 minimum data or enable set-up (ns) 3 4 6 7 minimum data or enable hold (ns) 0.5 1 1 2 maximum flag delay (ns) 8 10 15 20 active power supply current (i cc1 ) (ma) commercial 60 60 60 60 industrial 70 70 70 70 cy7c4801 cy7c4811 cy7c4821 cy7c4831 cy7c4841 cy7c4851 density double 256 x 9 double 512 x 9 double 1k x 9 double 2k x 9 double 4k x 9 double 8k x 9 package 64-pin tqfp 64-pin tqfp 64-pin tqfp 64-pin tqfp 64-pin tqfp 64-pin tqfp operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10% industrial [1] ? 40 c to +85 c 5v 10% notes: 1. t a is the ? instant on ? case temperature.
cy7c4801/4811/4821 cy7c4831/4841/4851 document #: 38-06005 rev. ** page 4 of 23 pin definitions signal name description i/o description da 0 ? 8 data inputs i data inputs for 9-bit bus db 0 ? 8 data inputs i data inputs for 9-bit bus qa 0 ? 8 data outputs o data outputs for 9-bit bus qb 0 ? 8 data outputs o data outputs for 9-bit bus wena1 wenb1 write enable 1 i wena1 and wenb1 become the only write enables when the device is configured to have programmable flags. data is written on a low-to-high transition of wclk when (wena1 ,wenb1 ) is low and (ffa ,ffb ) is high. if the fifo is configured to have two write enables, data is written on a low-to-high transition of wclk when (wena1 ,wenb1 ) is low and (wena2/lda ,wenb2/ldb ) and (ffa ,ffb ) are high. wena2/lda wenb2/ldb dual mode pin write enable 2 i if high at reset, this pin operates as a second write enable. if low at reset, this pin operates as a control to write or read the programmable flag offsets. (wena1 ,wenb1 ) must be low and (wena2/lda ,wenb2/ldb ) must be high to write data into the fifo. data will not be written into the fifo if the (ffa ,ffb ) is low. if the fifo is configured to have programmable flags, (wena2/lda ,wenb2/ldb ) is held low to write or read the program- mable flag offsets. load i rena1 rena2 renb1 renb2 read enable inputs i enables the device for read operation. wclka wcklb write clock i the rising edge clocks data into the fifo when (wena1 ,wenb1 ) is low and (wena2/lda ,wenb2/ldb ) is high and the fifo is not full. when (wena2/lda ,wenb2/ldb ) is asserted, wclk writes data into the programmable flag-offset register. rclka rclkb read clock i the rising edge clocks data out of the fifo when (rena1 ,renb1) and (rena2 ,renb2) are low and the fifo is not empty. when (wena2/lda, wenb2/ldb) is low, (rclka,rclkb) reads data out of the programmable flag-offset register. efa , efb empty flag o when (efa ,efb ) is low, the fifo is empty. (efa ,efb ) is synchronized to (rclka,rclkb). ffa,ffb full flag o when (ffa ,ffb ) is low, the fifo is full. (ffa,ffb ) is synchronized to (wclka,wclkb). paea paeb programmable almost empty o when (paea ,paeb) is low, the fifo is almost empty based on the almost empty offset value programmed into the fifo. pae is synchronized to rclk. pafa pafb programmable almost full o when (pafa ,pafb ) is low, the fifo is almost full based on the almost full offset value pro- grammed into the fifo. paf is synchronized to wclk. rsa rsb reset i resets device to empty condition. a reset is required before an initial read or write operation after power-up. oea oeb output enable i when (oea ,oeb) is low, the fifo ? s data outputs drive the bus to which they are connected. if (oea ,oeb ) is high, the fifo ? s outputs are in high z (high-impedance) state.
cy7c4801/4811/4821 cy7c4831/4841/4851 document #: 38-06005 rev. ** page 5 of 23 electrical characteristics over the operating range [2] 7c48x1-10 7c48x1-15 7c48x1-25 7c48x1-35 parameter description test conditions min. max. min. max. min. max. min. max. unit v oh output high voltage v cc = min., i oh = ? 2.0 ma 2.4 2.4 2.4 2.4 v v ol output low voltage v cc = min., i ol = 8.0 ma 0.4 0.4 0.4 0.4 v v ih input high voltage 2.0 v cc 2.0 v cc 2.0 v cc 2.0 v cc v v il input low voltage ? 0.5 0.8 ? 0.5 0.8 ? 0.5 0.8 ? 0.5 0.8 v i ix input leakage current v cc = max. ? 10 +10 ? 10 +10 ? 10 +10 ? 10 +10 a i os [3] output short circuit current v cc = max., v out = gnd ? 90 ? 90 ? 90 ? 90 ma i ozl i ozh output off, high z current oe > v ih , v ss < v o < v cc ? 10 +10 ? 10 +10 ? 10 +10 ? 10 +10 a i cc1 [4] active power supply current com ? l 60 60 60 60 ma ind 70 70 70 70 ma capacitance [5] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 10 pf c out output capacitance 10 pf ac test loads and waveforms [6, 7] notes: 2. see the last page of this specification for group a subgroup testing information. 3. test no more than one output at a time for not more than one second. 4. outputs open. tested at frequency = 20 mhz. 5. tested initially and after any design or process changes that may affect these parameters. 6. c l = 30 pf for all ac parameters except for t ohz . 7. c l = 5 pf for t ohz . 3.0v 5v output r1 1.1k ? r2 680 ? c l including jig and scope gnd 90% 10% 90% 10% 3ns 3 ns output 1.91v equivalent to: th venin equivalent 48x1 ? 4 420 ? all input pulses 48x1 ? 5
cy7c4801/4811/4821 cy7c4831/4841/4851 document #: 38-06005 rev. ** page 6 of 23 switching characteristics over the operating range 7c48x1-10 7c48x1-15 7c48x1-25 7c48x1-35 parameter description min. max. min. max. min. max. min. max. unit f s clock cycle frequency 100 66.7 40 28.6 mhz t a data access time 2 8 2 10 2 15 2 20 ns t clk clock cycle time 10 15 25 35 ns t clkh clock high time 4.5 6 10 14 ns t clkl clock low time 4.5 6 10 14 ns t ds data set-up time 3.5 4 6 7 ns t dh data hold time 0.5 1 1 2 ns t ens enable set-up time 3.5 4 6 7 ns t enh enable hold time 0.5 1 1 2 ns t rs reset pulse width [8] 10 15 25 35 ns t rss reset set-up time 8 10 15 20 ns t rsr reset recovery time 8 10 15 20 ns t rsf reset to flag and output time 10 15 25 35 ns t olz output enable to output in low z [9] 0 0 0 0 ns t oe output enable to output valid 3 7 3 8 3 12 3 15 ns t ohz output enable to output in high z [9] 3 7 3 8 3 12 3 15 ns t wff write clock to full flag 8 10 15 20 ns t ref read clock to empty flag 8 10 15 20 ns t paf clock to programmable almost-full flag 8 10 15 20 ns t pae clock to programmable almost-full flag 8 10 15 20 ns t skew1 skew time between read clock and write clock for empty flag and full flag 5 6 10 12 ns t skew2 skew time between read clock and write clock for almost-empty flag and almost-full flag 15 15 18 20 ns notes: 8. pulse widths less than minimum values are not allowed. 9. values guaranteed by design, not currently tested.
cy7c4801/4811/4821 cy7c4831/4841/4851 document #: 38-06005 rev. ** page 7 of 23 switching waveforms notes: 10. t skew1 is the minimum time between a rising (rclka,rclkb) edge and a rising (wclka,wclkb) edge to guarantee that (ffa ,ffb ) will go high during the current clock cycle. if the time between the rising edge of (rclka,rclkb) and the rising edge of (wclka,wclkb) is less than t skew1 , then (ffa ,ffb ) may not change state until the next (wclka,wclkb) rising edge. 11. t skew1 is the minimum time between a rising (wclka,wclkb) edge and a rising (rclka,rclkb) edge to guarantee that (efa ,efb ) will go high during the current clock cycle. it the time between the rising edge of (wclka,wclkb) and the rising edge of rclk is less than t skew1 , then (efa ,efb ) may not change state until the next (rclka,rclkb) rising edge. write cycle timing t clkh t clkl no operation t ds t skew1 t ens wena1 t clk t dh t wff t wff t enh wclka (wclkb) da 0 ? da 8 ffa (ffb ) rena1 , renb2 rclka (rclkb) 48x1 ? 6 no operation wena2(wenb2) (if applicable) (wenb1 ) (renb1 , renb2 ) (db 0 ? db 8 ) [10] read cycle timing t clkh t clkl no operation t skew1 t clk t ohz t ref t ref t oe t ens t olz t a t enh valid data 48x1 ? 7 efa ( efb ) wclka,wclkb oea (oeb) wena2(wenb2) qa 0 ? qa 8 (qb 0 ? qb 8 ) [11] (renb1 ,renb2 ) rena1 ,rena2 wena1 (wenb1 ) rclka (rclkb)
cy7c4801/4811/4821 cy7c4831/4841/4851 document #: 38-06005 rev. ** page 8 of 23 notes: 12. the clocks (rclka,rclkb, wclka,wclkb) can be free-running during reset. 13. after reset, the outputs will be low if (oea ,oeb) = 0 and three-state if (oea ,oeb) =1. 14. holding (wena2/lda ,wenb2/ldb ) high during reset will make the pin act as a second enable pin. holding(wena2/lda ,wenb2/ldb ) low during reset will make the pin act as a load enable for the programmable flag offset registers. switching waveforms (continued) reset timing t rs t rsr qa 0 ? qa 8 rsa (rsb ) t rsf t rsf t rsf oea (oeb )=1 oea (oeb )=0 rena1 , rena2 (renb1 ,renb2) efa , paea ffa , pafa 48x1 ? 8 t rss t rsr t rss t rsr t rss wena2/lda wena1 (wenb1 ) (wenb2/ldb ) (efb , paeb) (ffb , pafb) (qb 0 ? qb 8 ) [12] [ 13 ] [14]
cy7c4801/4811/4821 cy7c4831/4841/4851 document #: 38-06005 rev. ** page 9 of 23 notes: 15. when t skew1 > minimum specification, t frl (maximum) = t clk + t skew1 . when t skew1 < minimum specification, t frl (maximum) = either 2*t clk + t skew1 or t clk + t skew1 . the latency timing applies only at the empty boundary (efa , efb = low). 16. the first word is available the cycle after (efa , efb) goes high, always. switching waveforms (continued) (renb1 ,renb2) d 0 (firstvalid write) first data word latency after reset with simultaneous read and write t skew1 wena1 (wenb1 ) wclka,wclkb qa 0 ? qa 8 efa (efb ) rena1 , rena2 oea(oeb) t oe t ens t olz t ds rclka(rclkb) t ref t a t frl d 1 d 2 d 3 d 4 d 0 d 1 da 0 ? da 8 48x1 ? 9 t a wena2(wenb2) (if applicable) (db 0 ? db 8 ) (qb 0 ? qb 8 ) [ 15 ] [ 16 ]
cy7c4801/4811/4821 cy7c4831/4841/4851 document #: 38-06005 rev. ** page 10 of 23 switching waveforms (continued) wena2(wenb2) (if applicable) data write2 data write1 t ens t skew1 data in output register empty flag timing wena1 (wenb1 ) wclka,wclkb qa 0 ? qa 8 efa (efb ) rena1 , rena2 (renb1 ,renb2) oea (oeb ) t ds t enh rclka(rclkb) t ref t a t frl da 0 ? da 8 data read t skew1 t frl t ref t ds t ens t enh 48x1 ? 10 t ens t enh t ens t enh t ref low (db 0 ? db 8 ) (qb 0 ? qb 8 ) [15] [15]
cy7c4801/4811/4821 cy7c4831/4841/4851 document #: 38-06005 rev. ** page 11 of 23 switching waveforms (continued) full flag timing qa 0 ? qa 8 rena1 , rena2 (renb1 ,renb2) wena1 (wenb1 ) wena2(wenb2) (if applicable) da 0 ? da 8 next data read data write no write data in output register ffa (ffb ) wclka,wclkb oea (oeb ) rclka(rclkb) t a data read t skew1 t ds t ens t enh t wff t a t skew1 t ens t enh t wff data write no write t wff low 48x1 ? 11 no write (db 0 ? db 8 ) (qb 0 ? qb 8 ) [10] [10]
cy7c4801/4811/4821 cy7c4831/4841/4851 document #: 38-06005 rev. ** page 12 of 23 notes: 17. t skew2 is the minimum time between a rising (wclka,wclkb) and a rising (rclka,rclkb) edge for (paea ,paeb ) to change state during that clock cycle. if the time between the edge of (wclka,wclkb) and the rising (rclka,rclkb) is less than t skew2 , then (paea ,paeb ) may not change state until the next rclk. 18. (paea,paeb) offset = n. 19. if a read is preformed on this rising edge of the read clock, there will be empty + (n-1) words in the fifo when (paea ,paeb ) goes low. 20. if a write is performed on this rising edge of the write clock, there will be full - (m-1) words of the fifo when (pafa,pafb ) goes low. 21. (pafa,pafb) offset = m. 22. 256-m words in fifo for cy7c4801, 512-m words for cy7c4811, 1024-m words for cy7c4821, 2048-m words for cy7c4831, 4096-m wor ds for cy7c4841, 8192-m words for cy7c4851. 23. t skew2 is the minimum time between a rising (rclka,rclkb) edge and a rising (wclka,wclkb) edge for (pafa,pafb ) to change during that clock cycle. if the time between the rising edge of (rclka,rclkb) and the rising edge of (wclka,wclkb) is less than t skew2 , then (pafa,pafb ) may not change state until the next (wclka,wclkb). switching waveforms (continued) t enh programmable almost empty flag timing t clkh t ens t clkl t pae n + 1 words in fifo 48x1 ? 12 t enh t ens t enh t ens t pae t skew2 [17] wclka,wclkb paea (paeb ) rclka(rclkb) rena1 , rena2 (renb1 ,renb2) wena1 (wenb1 ) wena2(wenb2) (if applicable) note 18 note 19 t enh programmable almost full flag timing t clkh t ens full ? m words in fifo t clkl t ens full ? m+1 words in fifo 48x1 ? 13 t enh t ens t enh t ens t paf t skew2 t paf [22] [23] wclka,wclkb pafa (pafb ) rclka(rclkb) rena1 , rena2 (renb1 ,renb2) wena1 (wenb1 ) wena2(wenb2) (if applicable) note 20 note 21
cy7c4801/4811/4821 cy7c4831/4841/4851 document #: 38-06005 rev. ** page 13 of 23 switching waveforms (continued) t enh write programmable registers wena2/lda t clkh t ens t clkl pae offset lsb t ens paf offset msb t clk t ds t dh 48x1 ? 14 pae offset msb paf offset lsb wclka,wclkb da 0 ? da 8 wena1 (wenb1 ) (wenb2/ldb ) (db 0 ? db 8 ) paf offset msb paf offset lsb t enh read programmable registers t clkh t ens t clkl pae offset lsb t ens pae offset msb t clk unknown t a 48x1 ? 15 wena2/lda rclka(rclkb) qa 0 ? qa 8 rena1 , rena2 (renb1 ,renb2) (wenb2/ldb ) (qb 0 ? qb 8 )
cy7c4801/4811/4821 cy7c4831/4841/4851 document #: 38-06005 rev. ** page 14 of 23 architecture the cy7c48x1 functions as two independent fifos in a single package, each with its own separate set of controls. the device con- sists of two arrays of 256 to 8k words of 9 bits each (imple- mented by a dual-port array of sram cells), two read pointers, two write pointers, control signals (rclka, rclkb, wclka, wclkb, rena1 , renb1 , rena2 , renb2 , wena1 , wenb1 , wena2, wenb2, rsa , rsb ), and flags (efa ,efb , paea ,paeb , pafa ,pafb , ffa ,ffb ). resetting the fifo upon power-up, the fifo must be reset with a reset (rsa , rsb ) cycle. this causes the fifo to enter the empty condition signi- fied by (efa ,efb) being low. all data outputs (qa 0 ? 8, qb 0 ? 8 ) go low t rsf after the rising edge of rsa , rsb . in order for the fifo to reset to its default state, a falling edge must occur on (rsa ,rsb ) and the user must not read or write while (rsa ,rsb ) is low. all flags are guaranteed to be valid t rsf after (rsa ,rsb) is taken low. fifo operation when the (wena1 ,wenb1 ) signal is active low and (wena2,wenb2) is active high, data present on the (da 0 ? 8, db 0 ? 8 ) pins is written into the fifo on each rising edge (wclka,wclkb) of the (wclka,wclkb) signal. similarly, when the (rena1 ,renb1 ) and (rena2 ,renb2 ) signals are active low, data in the fifo memory will be presented on the (qa 0 ? 8, qb 0 ? 8 ) outputs. new data will be presented on each rising edge of (rclka,rclkb) while (rena1 ,renb1 ) and (rena2 ,renb2 ) are active. (rena1 ,renb1 ) and (rena2 ,renb2 ) must set up t ens be- fore (rclka,rclkb) for it to be a valid read function. (wena1 ,wenb1 ) and (wena2,wenb2) must occur t ens before (wclka,wclkb) for it to be a valid write function. an output enable (oea ,oeb ) pin is provided to three-state the (qa 0 ? 8, qb 0 ? 8 ) outputs when (oea ,oeb ) is asserted. when (oea ,oeb ) is enabled (low), data in the output register will be avail- able to the (qa 0 ? 8, qb 0 ? 8 ) outputs after toe. the fifo contains overflow circuitry to disallow additional writes when the fifo is full, and underflow circuitry to disallow additional reads when the fifo is empty. an empty fifo maintains the data of the last valid read on its (qa 0 ? 8, qb 0 ? 8 ) outputs even after additional reads occur. write enable 1 (wena1 ,wenb1 ) - if the fifo is configured for programmable flags, write enable 1 (wena1 ,wenb1 ) is the only write enable control pin. in this configuration, when write enable 1 (wena1 ,wenb1 ) is low, data can be loaded into the input register and ram array on the low-to-high transition of every write clock (wclka,wclkb). data is stored is the ram array sequentially and independently of any on-going read operation. write enable 2/load (wena2/lda , wenb2/ldb ) - this is a dual-purpose pin. the fifo is configured at reset to have programmable flags or to have two write enables, which allows for depth expansion. if write enable 2/load (wena2/lda, wenb2/ldb ) is set active high at reset (rsa ,rsb =low), this pin operates as a second write enable pin. if the fifo is configured to have two write enables, when write enable 1 (wena1 ,wenb1 ) is low and write enable 2/load (wena2/lda , wenb2/ldb ) is high, data can be loaded into the input register and ram array on the low-to-high transition of every write clock (wclka,wclkb). data is stored in the ram array se- quentially and independently of any on-going read operation. programming when (wena2/lda, wenb2/ldb ) is held low during reset, this pin is the load (lda ,ldb ) enable for flag offset programming. in this configuration, (wena2/lda , wenb2/ldb ) can be used to access the four 8-bit offset registers contained in the cy7c48x1 for writing or reading data to these registers. when the device is configured for programmable flags and both (wena2/lda, wenb2/ldb ) and (wena1 ,wenb1 ) are low, the first low-to-high transition of (wclka,wclkb) writes data from the data inputs to the empty offset least significant bit (lsb) register. the second, third, and fourth low-to-high transitions of (wclka,wclkb) store data in the empty offset most significant bit (msb) register, full offset lsb register, and full offset msb register, respectively, when (wena2/lda , wenb2/ldb ) and (wena1 ,wenb1 ) are low. the fifth low-to-high transition of (wclka,wclkb) while (wena2/lda , wenb2/ldb ) and (wena1 ,wenb1 ) are low writes data to the empty lsb register again. figure 1 shows the register sizes and default values for the various device types. it is not necessary to write to all the offset registers at one time. a subset of the offset registers can be written; then by bringing the (wena2/lda , wenb2/ldb ) input high, the fifo is returned to normal read and write operation. the next time (wena2/lda, wenb2/ldb ) is brought low, a write operation stores data in the next offset register in sequence. the contents of the offset registers can be read to the data outputs when (wena2/lda , wenb2/ldb ) is low and both (rena1 ,renb1 ) and (rena2 ,renb2 ) are low. low-to-high transitions of (rclka,rclkb) read register contents to the data out- puts. writes and reads should not be preformed simultaneously on the offset registers.
cy7c4801/4811/4821 cy7c4831/4841/4851 document #: 38-06005 rev. ** page 15 of 23 programmable flag (paea ,paeb , pafa,pafb ) operation whether the flag offset registers are programmed as de- scribed in table 1 or the default values are used, the programmable almost-empty flag (paea ,paeb ) and programmable almost-full flag (pafa ,pafb ) states are determined by their corresponding offset registers and the difference between the read and write pointers. the number formed by the empty offset least significant bit register and empty offset most significant register is referred to as n and determines the operation of (paea ,paeb ). (paea ,paeb ) is synchronized to the low-to-high transition of rclk by one flip-flop and is low when the fifo contains n or fewer unread words. (paea ,paeb ) is set high by the low-to-high tran- sition of rclk when the fifo contains (n+1) or greater unread words. the number formed by the full offset least significant bit regis- ter and full offset most significant bit register is referred to as m and determines the operation of (pafa ,pafb ). (paea ,paeb ) is synchronized to the low-to-high transition of (wclka,wclkb) by one flip-flop and is set low when the number of unread words in the fifo is greater than or equal to cy7c4801 (256 ? m), cy7c4811 (512 ? m), cy7c4821 (1k ? m), cy7c4831 (2k ? m), cy7c4841 (4k ? m), and cy7c4851 (8k ? m). (pafa ,pafb ) is set high by the low-to-high transition of (wclka,wclkb) when the number of available memory locations is greater than m. notes: 24. the same selection sequence applies to reading form the registers. ren1 and ren2 are enabled and a read is performed on the low- to-high transition of rclk. figure 1. offset register location and default values. 256 x 9 x 2 512 x 9 x 2 8 0 8 0 8 0 8 0 1k x 9 x 2 2k x 9 x 2 4k x 9 x 2 8k x 9 x 2 (msb) 0 (msb) 0 7 1 7 1 8 0 8 0 8 0 8 0 (msb) 00 (msb) 00 7 1 7 1 8 0 8 0 8 0 8 0 (msb) 000 (msb) 000 7 2 7 2 8 0 8 0 8 0 8 0 empty offset (lsb) reg. default value = 007h full offset (lsb) reg default value = 007h (msb) 0000 (msb) 0000 7 3 7 3 empty offset (lsb) reg. default value = 007h full offset (lsb) reg default value = 007h empty offset (lsb) reg. default value = 007h full offset (lsb) reg default value = 007h empty offset (lsb) reg. default value = 007h full offset (lsb) reg default value = 007h 8 0 8 0 8 0 8 0 empty offset (lsb) reg. default value = 007h full offset (lsb) reg default value = 007h (msb) 00000 (msb) 00000 7 4 7 4 8 0 8 0 8 0 8 0 7 7 full offset (lsb) reg default value = 007h empty offset (lsb) reg. default value = 007h table 1. writing the offset registers. ld wen wclk [24] selection 0 0 empty offset (lsb) empty offset (msb) full offset (lsb) full offset (msb) 0 1 no operation 1 0 write into fifo 1 1 no operation
cy7c4801/4811/4821 cy7c4831/4841/4851 document #: 38-06005 rev. ** page 16 of 23 flag operation the cy7c48x1 devices provide four flag pins to indicate the condition of the fifo contents. empty, full, (paea ,paeb ), and (pafa ,pafb ) are synchronous. full flag the full flag (ffa ,ffb ) will go low when the device is full. write operations are inhibited whenever (ffa ,ffb ) is low regardless of the state of (wena1 ,wenb1 ) and (wena2/lda, wenb2/ldb ). (ffa ,ffb ) is synchronized to (wclka,wclkb), i.e., it is exclusively updated by each rising edge of (wclka,wclkb). empty flag the empty flag (efa ,efb ) will go low when the device is empty. read operations are inhibited whenever (efa ,efb ) is low, regard- less of the state of (rena1 ,renb1 ) and (rena2 ,renb2 . (efa ,efb ) is synchronized to (rclka,rclkb), i.e., it is exclusively full flag. table 2. status flags. number of words in fifo ff paf pae ef cy7c4801 cy7c4811 cy7c4821 0 0 0 h h l l 1 to n [25] 1 to n [25] 1 to n [25] h h l h (n+1) to (256-(m+1)) (n+1) to (512-(m+1)) (n+1) to (1024 ? (m+1)) h h h h (256 ? m) [26] to 255 (512 ? m) [26] to 511 (1024 ? m) [26] to 1023 h l h h 256 512 1024 l l h h number of words in fifo ff paf pae ef cy7c4831 cy7c4841 cy7c4851 0 0 0 h h l l 1 to n [25] 1 to n [25] 1 to n [25] h h l h (n+1) to (2048 ? (m+1)) (n+1) to (4096 ? (m+1)) (n+1) to (8192 ? (m+1)) h h h h (2048 ? m) [26] to 2047 (4096 ? m) [26] to 4095 (8192 ? m) [26] to 8191 h l h h 2048 4096 8192 l l h h notes: 25. n =empty offset (n=7 default value). 26. m = full offset (m=7 default value).
cy7c4801/4811/4821 cy7c4831/4841/4851 document #: 38-06005 rev. ** page 17 of 23 single device configuration when fifo a(b) is in a single device configuration, the read enable 2 rena2 (renb2 ) control input can be grounded (see figure 2 ). in this configuration, the write enable2/load (wena2/lda ,wenb2/ldb ) pin is set low at reset so that the pin operates as a control to load and read the programma- ble flag offsets. figure 2. block diagram of 256 x 9,512 x 9,1024 x 9,2048 x 9,4096 x 9,8192 x 9 double sync fifo used in a single device configuration. empty flag(efa ,efb ) 48x1 ? 16 write clock (wclka,wclkb) write enable 1 (wena1 ,wenb1 ) write enable2/load(wena2/lda ,wenb/ldb ) (pafa ,pafb ) full flag (ffa ,ffb ) cy7c4801 data in da 0 ? da 8 (db 0 ? db 8 ) reset (rsa ,rsb ) read clock (rclka,rclkb) read enable 1 (rena1 ,renb1 ) output enable (oea ,oeb ) programmable(paea ,paea ) read enable 2 (rena2 ,renb 2) cy7c4811 cy7c4821 cy7c4831 cy7c4841 cy7c4851 data out qa 0 ? qa 8 (qb 0 ? qb 8 ) programmable
cy7c4801/4811/4821 cy7c4831/4841/4851 document #: 38-06005 rev. ** page 18 of 23 width expansion configuration word width may be increased simply by connecting the corre- sponding input control signals of fifos a and b. a composite flag should be created for each of the end-point status flags efa and efb , also ffa and ffb . the partial status flags paea , pafb , pafa , pafb can be detected from any one de- vice. figure 3 demonstrates an 18-bit word width using the two fifos contained in one cy7c4801/4811/4821/4831/4841 /4851. any word width can be attained by adding additional cy7c4801/4811/4821/4831/4841/4851s. when the cy7c4801/4811/4821/4831/4841/4851 is in a width expansion configuration, the read enable 2 (rena2 and renb2) control unputs can be grounded (see figure 3 ). in this configuration, the write enable 2/load (wena2/lda ,wenb2/ldb ) pins are set low at reset so that the pin operates as a control to load and read the programma- ble flag offsets. figure 3. block diagram of two fifos contained in one cy7c4801/4811/4821/4831/4841/4851 configured for an 18-bit width-expansion. write enable wena (rena2 ) 48x1 ? 17 ff ef wclka write enable 2/load wen2/ld full flag ffa 9 18 reset (rsa ) 9 reset (rsb ) rclkb read enable renb1 output enable oeb empty flag efa 9 9 18 read enable 2 efb ffb read enable 2 (renb2 ) ram array a ram array b 256 x 9 512 x 9 1024 x 9 2048 x 9 4096 x 9 8192 x 9 256 x 9 512 x 9 1024 x 9 2048 x 9 4096 x 9 8192 x 9 rclka wclkb writeclock readclock rena1 wenb1 oea wenb2/ldb reset 9 d 0 ? d 17 q 0 ? q 17
cy7c4801/4811/4821 cy7c4831/4841/4851 document #: 38-06005 rev. ** page 19 of 23 bidirectional configuration the two fifos of the cy7c4801/4811/4821/4831/4841/4851 can be used to buffer data flow in two directions. in the exam- ple that follows, processor a can write data to processor b via fifo a, and, in turn, processor b can write processor a via fifo b. depth expansion cy7c4801/4811/4821/4831/4841/4851can be adapted to ap- plications that require greater than 256/512/1024/2048/4096/ 8192 words. the existence of dual enable pins on the read and write ports allow depth expansion. the write enable 2/load (wena2, wenb2) pins are used as a second write enables in a depth expansion configuration, thus the programmable flags are set to the default values. depth expansion is possible by using one enable input for system control while the other en- able input is controlled by expansion logic to direct the flow of data. a typical application would have the expansion logic al- ternate data access from one device to the next in a sequential manner. the cy7c4801/4811/4821/4831/4841/ 4851 oper- ates in the depth expansion configuration when the following conditions are met: 1. wena2/lda and wenb2/ldb pins are held high during reset so that these pins operate as second write enables. 2. external logic is used to control the flow of data. figure 4. block diagram of bidirectional configuration. 9 cy7c4801 cy7c4811 cy7c4821 cy7c4831 cy7c4841 cy7c4851 ram array a ram array b wena2 rena2 rclka wclka wena1 da 0 ? da 8 oea rena1 qa 0 ? qa 8 wenb2 renb2 rclkb wclkb wenb1 db 0 ? db 8 oeb renb1 qb 0 ? qb 8 v cc ram processor a clock address control data control logic control logic v cc 9-bit bus 9 9 9 9 9 9 9-bit bus processor a clock address control data 9 ram 48x1 ? 18
cy7c4801/4811/4821 cy7c4831/4841/4851 document #: 38-06005 rev. ** page 20 of 23 ordering information double 256x9 fifo speed (ns) ordering code package name package type operating range 10 cy7c4801-10ac a65 64-lead thin quad flatpack commercial cy7c4801-10ai a65 64-lead thin quad flatpack industrial 15 cy7c4801-15ac a65 64-lead thin quad flatpack commercial cy7c4801-15ai a65 64-lead thin quad flatpack industrial 25 cy7c4801-25ac a65 64-lead thin quad flatpack commercial cy7c4801-25ai a65 64-lead thin quad flatpack industrial 35 cy7c4801-35ac a65 64-lead thin quad flatpack commercial cy7c4801-35ai a65 64-lead thin quad flatpack industrial double 512x9 fifo speed (ns) ordering code package name package type operating range 10 cy7c4811-10ac a65 64-lead thin quad flatpack commercial cy7c4811-10ai a65 64-lead thin quad flatpack industrial 15 cy7c4811-15ac a65 64-lead thin quad flatpack commercial cy7c4811-15ai a65 64-lead thin quad flatpack industrial 25 cy7c4811-25ac a65 64-lead thin quad flatpack commercial cy7c4811-25ai a65 64-lead thin quad flatpack industrial 35 cy7c4811-35ac a65 64-lead thin quad flatpack commercial CY7C4811-35AI a65 64-lead thin quad flatpack industrial double 1kx9 fifo speed (ns) ordering code package name package type operating range 10 cy7c4821-10ac a65 64-lead thin quad flatpack commercial cy7c4821-10ai a65 64-lead thin quad flatpack industrial 15 cy7c4821-15ac a65 64-lead thin quad flatpack commercial cy7c4821-15ai a65 64-lead thin quad flatpack industrial 25 cy7c4821-25ac a65 64-lead thin quad flatpack commercial cy7c4821-25ai a65 64-lead thin quad flatpack industrial 35 cy7c4821-35ac a65 64-lead thin quad flatpack commercial cy7c4821-35ai a65 64-lead thin quad flatpack industrial
cy7c4801/4811/4821 cy7c4831/4841/4851 document #: 38-06005 rev. ** page 21 of 23 ordering information (continued) double 2kx9 fifo speed (ns) ordering code package name package type operating range 10 cy7c4831-10ac a65 64-lead thin quad flatpack commercial cy7c4831-10ai a65 64-lead thin quad flatpack industrial 15 cy7c4831-15ac a65 64-lead thin quad flatpack commercial cy7c4831-15ai a65 64-lead thin quad flatpack industrial 25 cy7c4831-25ac a65 64-lead thin quad flatpack commercial cy7c4831-25ai a65 64-lead thin quad flatpack industrial 35 cy7c4831-35ac a65 64-lead thin quad flatpack commercial cy7c4831-35ai a65 64-lead thin quad flatpack industrial double 4kx9 fifo speed (ns) ordering code package name package type operating range 10 cy7c4841-10ac a65 64-lead thin quad flatpack commercial cy7c4841-10ai a65 64-lead thin quad flatpack industrial 15 cy7c4841-15ac a65 64-lead thin quad flatpack commercial cy7c4841-15ai a65 64-lead thin quad flatpack industrial 25 cy7c4841-25ac a65 64-lead thin quad flatpack commercial cy7c4841-25ai a65 64-lead thin quad flatpack industrial 35 cy7c4841-35ac a65 64-lead thin quad flatpack commercial cy7c4841-35ai a65 64-lead thin quad flatpack industrial double 8kx9 fifo speed (ns) ordering code package name package type operating range 10 cy7c4851-10ac a65 64-lead thin quad flatpack commercial cy7c4851-10ai a65 64-lead thin quad flatpack industrial 15 cy7c4851-15ac a65 64-lead thin quad flatpack commercial cy7c4851-15ai a65 64-lead thin quad flatpack industrial 25 cy7c4851-25ac a65 64-lead thin quad flatpack commercial cy7c4851-25ai a65 64-lead thin quad flatpack industrial 35 cy7c4851-35ac a65 64-lead thin quad flatpack commercial cy7c4851-35ai a65 64-lead thin quad flatpack industrial
cy7c4801/4811/4821 cy7c4831/4841/4851 document #: 38-06005 rev. ** page 22 of 23 ? cypress semiconductor corporation, 1997. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. package diagram 64-lead thin plastic quad flat pack a65
cy7c4801/4811/4821 cy7c4831/4841/4851 document #: 38-06005 rev. ** page 23 of 23 document title: cy7c4801/4811/4821/cy7c4831.4841/4851 256/512/1k/2k/4k/8k x9 x2 double sync (tm) fifos document number: 38-06005 rev. ecn no. issue date orig. of change description of change ** 106466 07/11/01 szv change from spec number: 38-00538 to 38-06005

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